As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), gate-all-around transistor devices (GAA), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues. HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure. An example is a Si/SiGe superlattice stack composed of alternating silicon and silicon:germanium alloy (SiGe) layers, and arranged in a vertical configuration having an overall fin shape. The formation of final HGAA structures according to known techniques involves selectively removing the silicon:germanium layer (in the case of silicon devices), to form nanowire structures made of silicon, from which structures, the HGAA transistor is fabricated.
These known approaches entail several drawbacks. Including a limitation on the number of nanowires fabricated in a stack, due to mechanical instability of the fins. Another drawback is a relatively low device yield resulting from the strain in silicon nanowires grown in a Si/SiGe superlattice. A further drawback is the inherent difficulty in forming a SiGe channel for PFET devices.
With respect to these and other considerations, the present disclosure is provided.